Recently, Professor Guangjun WEN's team from the School of Information and Communication Engineering, in collaboration with Professor Sun Nan's team from the University of Texas at Austin, published a research paper titled "A 0.029-mm² 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer" in the international flagship journal IEEE Journal of Solid-State Circuits. The first author of the paper is Jiaxin LIU, a doctoral student under the supervision of Professor Guangjun WEN, and the first author's affiliation is the School of Information and Communication Engineering at the University of Electronic Science and Technology of China (UESTC). This marks the second publication of Professor Guangjun WEN's team in this journal. Including this paper, UESTC, as the first author's affiliation, has published seven papers in JSSC. Professor Kai KANG's team from the School of Electronic Engineering has contributed three papers, Professor Qiang LI's team one paper, and Professor Jianhao HU's team from the State Key Laboratory of Electromagnetic Environmental Effects on Electronics and Information Systems one paper. Since its inception in 1966, JSSC has published over 12,300 papers, and mainland China has contributed more than 50 papers to this journal.
(a) Chip micrographs and layouts
(b) Measured spectrum characteristics of the chip
The paper introduces a novel hybrid structure continuous-time ΔΣ ADC architecture that utilizes a passive noise-shaping SAR ADC as the quantizer for the continuous-time ΔΣ ADC. This innovative approach combines the advantages of continuous-time and discrete-time architectures. The proposed design achieves third-order noise shaping with only one operational transconductance amplifier (OTA), significantly reducing the complexity, power consumption, and chip area of the ADC circuit. It enhances ADC stability while retaining anti-aliasing filtering characteristics. The passive noise-shaping SAR quantizer presented in the paper is entirely based on switch capacitor circuits, effectively reducing non-ideal factors such as in-band quantization noise and comparator noise by 24 dB. Compared to classical SAR ADCs, the proposed design only adds two switches, two capacitors, and two differential input pairs of comparators, resulting in a simpler structure. Compared to existing similar passive noise-shaping SAR ADCs, it significantly reduces the attenuation of the passive integrator path, effectively lowers the equivalent input noise of the ADC, and reduces the total capacitor area, DAC capacitor area, and comparator power consumption by 2.4 times, 5 times, and 40%, respectively, under the same thermal noise budget. The ADC chip was fabricated using a 40nm CMOS process, and the measured energy efficiency figure of merit is 17 fJ/conversion step, reaching a world-class level. The designed ADC chip has the advantages of small area, high stability, and low power consumption, making it promising for applications in the Internet of Things (IoT), wireless communication, and other signal processing fields.
Jiaxin LIU is a doctoral student from the 2013 class of the School of Information and Communication Engineering. From 2015 to 2017, she was sent to the University of Texas at Austin for joint training in Professor Sun Nan's team. After completing her Ph.D. in December 2018, she worked as a postdoctoral researcher at Tsinghua University. Her primary research focus is on analog and mixed-signal integrated circuit technology. In addition to this paper, the doctoral student has published multiple research papers in top journals in the field of circuits and systems, such as IEEE Transactions on Circuits and Systems I: Regular Papers, and top international conferences on solid-state circuits, such as IEEE International Solid-State Circuits Conference and IEEE Symposium on VLSI Technology and Circuits. During her time at the university, she received national scholarships, Guorui scholarships, first-class academic scholarships, and won first prize in the Chip Original Cup Circuit Design Competition.
Professor Guangjun WEN's research team, leading the RF integrated circuits and systems research center, is mainly engaged in research on integrated circuits, RFID, satellite navigation, sensor networks, the Internet of Things (IoT), wireless power transmission, and simultaneous wireless information and power transfer systems. The team has developed a series of products with independent intellectual property rights, including Beidou navigation terminal RF chips, ultra-high-frequency RFID tag chips, multi-protocol ultra-high-frequency RFID readers, and cellular IoT systems. Some of these products have achieved industrial applications. The team has published over 500 papers in internationally renowned journals such asNature Communications,IEEE Commun. Surv. Tut.,Adv. Opt. Mater.,Phys. Rev. Appl.,IEEE JSSC,IEEE Trans CAS/MTT/AP,APL,Optics Express, as well as international conferences including VLSI, CELO, and IEEE International Microwave Symposium/Antennas and Propagation Symposium. Among these publications, over 200 papers have been included in the SCI database. The team has been granted more than 50 patents, received four provincial and ministerial-level science and technology awards, and one outstanding Ph.D. thesis award from the China Electronics Education Society.
Paper Link: https://ieeexplore.ieee.org/document/8543627
