由信息与通信工程学院主办的“信通论坛”本次邀请到新加坡南洋理工大学Tony教授，与我校师生共同探讨Ultra-low Power/Energy SRAM Design for Emerging Application。具体安排如下，欢迎感兴趣的师生参加。
一、主 题：Ultra-low Power/Energy SRAM Design for Emerging Application
二、主讲人：Prof.Tony Kim(新加坡南洋理工大学)
三、时 间：2019年7月3日（周三）10:00-12:00
四、地 点：清水河校区科研楼B302
五、主持人：信息与通信工程学院 周军 博士
六、内容简介：
Recently, various ultra-low power applications such as Internet-of-Things (IoT), wearable devices, and biomedical devices have emerged opening up a new domain of integrated circuits design. In these applications, ultra-low voltage circuit techniques for improving the power and energy efficiencies have been the main research focus. One of the most challenging functional blocks in ultra-low power systems is memory where SRAMs are dominantly employed. Since SRAMs occupy majority of the power in those systems, design of ultra-low power SRAMs is a critical task for power and energy efficiencies. One of the most popular SRAM design methodology for ultra-low power applications is using aggressively scaled supply voltage. However, this deteriorates various SRAM design parameters such as stability, sensing margin, write margin, etc. Various techniques for ultra-low voltage SRAMs have been reported to tackle the limitations at ultra-low voltage operation. This tutorial will provide the basics in ultra-low voltage SRAMs followed by the trend in various state-of-the-art ultra-low voltage SRAMs. More detailed ultra-low voltage SRAM design works developed by the author’s group will also be explained. Finally, we will discuss future directions in ultra-low voltage SRAMs including various emerging non-volatile memory devices such as Flash, STTRAM, RRAM, etc.
七、主讲人简介：
Tony Tae-Hyoung Kim (M’06-SM'14) received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on circuit reliability, low power SRAM, and battery backed memory design, respectively. On November 2009, he joined Nanyang Technological University where he is currently an associate professor.
He received “Best Demo Award” ay APCCAS2016, “Low Power Design Contest Award” at ISLPED2016, best paper awards at 2014 and 2011 ISOCC, “AMD/CICC Student Scholarship Award” at IEEE CICC2008, Departmental Research Fellowship from Univ. of Minnesota in 2008, “DAC/ISSCC Student Design Contest Award” in 2008, “Samsung Humantec Thesis Award” in 2008, 2001, and 1999, and “ETRI Journal Paper of the Year Award” in 2005. He is an author/co-author of +150 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an Associate Editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and was the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.
八、主办单位：信息与通信工程学院
